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ADM1041
OrFET GATE DRIVE
When configured, this block provides a signal to turn on/off an
OrFET used in the output of paralleled power supplies. The gate
drive voltage of one of these FETs is typically 6 V to 10 V above
the output voltage. Since the output voltage of the ADM1041 is
limited, an external transistor needs to be used. The block
diagram shows an example of this approach. See Figure 21.
The F G output is an open-drain, N-channel MOSFET and is
normally high, which holds the OrFET off. When all the start-
up conditions are correct, Pin 19 is pulled low, which allows the
OrFET to turn on. The logic can also be configured as inverted
if a noninverting drive circuit is used.
A differential amplifier monitors the voltage across the OrFET
and has two major functions. First, during start-up, it allows the
OrFET to turn on with almost 0 V across it to avoid voltage
glitches on the bus. This applies to a hot bus or a cold bus. The
internal threshold can be configured from 20 mV to 50 mV
(negative), which is scaled up by the external voltage dividers.
Second, if a rectifier or filter capacitor fails during steady state
operation, it detects the resulting reverse voltage across the
OrFET’s on-resistance and turns off the OrFET before a voltage
dip appears on the bus. The internal threshold can be configured
from 100 mV to 250 mV (negative), which is also scaled up by
the external voltage dividers. A slightly larger filter capacitor
may be used on the voltage divider at Pin 6 to speed up this
function.
Figure 17 shows the typical response time of the ADM1041 to
such an event. In the plot, V FD is ramped down and the response
time of the F G pin to a reverse voltage event on the F D pin is
seen. This simulates the rectifier or filter capacitor failure
during steady state operation. When the F D voltage is below
1.9 V (2 V minus 100 mV threshold), the F G pin reacts. As can
be seen, the response time is approx 330 nsecs. This extremely
fast turn-off is vital in an n+1 power supply system configuration.
It ensures that the damaged power supply removes itself from
the system quickly. Figure 18 is the equivalent response time to
turn on the OrFET. As can be seen, there is a delay of approxi-
mately 500 ns before the FG pin ramps down to turn on the
OrFET, and therefore allow the power supply to contribute to the
system. This propagation delay is due mainly to internal amplifier
response limitations. The circuit in Figure 21 is used to generate
these plots. In this case, the resistor to VDD from the FG pin is
2 k?.
Figure 19 and Figure 20 show the OrFET turn-off time and
turn-on time when the F G pin polarity is inverted. As can be
seen, to turn off the OrFET, the V FG pin now transitions from
high to low. Also, its corresponding turn-on event occurs from a
low-to-high transition. The circuit in Figure 21 is used to
generate these plots.
Rev. A | Page 28 of 64
T TOTAL = 330ns
64%
T DELAY = 218ns T = 112ns
Figure 17. OrFET Turn-Off Time (Default Polarity)
T TOTAL = 506ns
Figure 18. OrFET Turn-On Time (Default Polarity)
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